Minimum 3-5 years professional experience in microelectronics custom layout
Good verbal and writing communication skills.
Background in custom Analog, Digital and Mixed-Signal Layout designs such asADC, DAC, oscillators, regulators, PLLs, op-amps, comparators, current mirrors, active-loads, voltage regulators, charge pumps, etc.
Capable of block or fullchip level floorplanning in Analog/Mixed-Signal design.
Strong problem solving ability.
Deep sub-micron process design experience. Up to 14nm is preferable.
Understanding of circuit principles as affected by layout such capacitance, speed, noise & electro migration.
Willing to travel and relocate.
Have done multiple tapeouts and proven record of designing complex ICs/IPs in state of the art CMOS process technologies and has successfully placed products/IPs into production, preferably multiple times.
High level proficiency in performing physical verification check (DRC, ERC, LVS, ANTENNA rules) with PVS/Calibre tools.
Experience with the following EDA tools: Cadence Virtuoso (Layout), PVS, Calibre Verification.
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T2-L5-2, Level 5, Tower 2, Jaya 33, No. 3, Jalan Prof. Khoo Kay Kim, Seksyen 13, 46200 Petaling Jaya, Selangor, MALAYSIA