Digital IC Design Engineer (RTL & FPGA)

REQUIREMENTS

Experience of 5 years and above in logic design and/or architecture.
Master’s degree or bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
Strong understanding of engineering design principles.
Strong background in ASIC design methodology and EDA tools (Cadence/Mentor Graphics/Synopsys) for simulation and verification, synthesis, P&R, formal verification and static timing analysis.
Strong coding skill in:
- Verilog/VHDL RTL and behavioral code
- System Verilog
Familiar with Linux Environment (including shell scripting and linux gnu tools).
Scripting language experience in perl, tcl, python, etc.).
Highly self-motivated and excellent in problem solving and time management skills.
Able to work independently and in a team environment.
Excellent written and verbal communication skills.

Job Description

RTL development and pre-Silicon RTL functional validation tests to verify system/IPs which will meet design requirements.
Creating test plans for RTL validation.
Defining and running system simulation models.
Finding and implementing corrective measures for failing RTL tests.
Analyzing and using results to modify testing.
Working with design/micro-architect/architect teams to define verification strategy, planning and execution, driving verification methodologies etc.
Create environment to verify and validate RTL
Experience in Zebu synthesis, compilation and synthesis.
Verify RTL through simulation simulation and Zebu Emulation flow
Obtain hw capture and analyze and fix RTL
Perl/Python scripting is a plus

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