SYMMID CORPORATION SDN BHD (625782-U)
B-G-11, JALAN SS6/20,
DATARAN GLOMAC,
KELANA JAYA,
47301 PETALING JAYA,
SELANGOR DARUL EHSAN,
MALAYSIA.

TEL: +603 7880 6040
FAX: +603 7880 6141
http://www.symmid.com




ASIC STATEMENT REQUEST FORM


1.0	Requestor information

Mr/Mrs/Ms:
Last Name:	
First Name:	
Company:	 
Title:	 	
Address: 
City:	    
State:	    
Postal Code: 	
Country:	    	
Email:	
Website:		
Phone No.:	
Fax No.:	

	
2.0	Product Application (Please specify):	
	

3.0	Design Engagement Model	

Select the design hand-off point for the project	
a.	Specification	
b.	Incomplete RTL	
c.	Complete RTL	
d.	Other (Please specify):		

Select the component manufacturing needs (if any) for the project
a.	Prototype wafer	
b:	Packaged prototype	
c:	Pilot manufacturing	
d:	Commercial Manufacturing (Specify volumes):		


4.0	Key Milestones and Target dates	
a:	Design Hand-off	
b:	Design Sign-off	
c:	Design Tape-out	
d:	Packaged Prototype delivered 	
e:	Pilot manufacturing delivered	
f:	Commercial manufacturing delivered		

 
5.0	Design Information	
	
5.1	Anticipated Design Style	
a:	Custom	
b:	Standard Cell	
c:	Gate Array	
d:	Other (Please specify):		

5.2	Anticipated Process Technology	
a:	0.25 .m logic	
b:	0.18 .m logic	
c:	0.13 .m logic	
d:	90 nm logic	
e:	Other (Please specify):		

5.3	Number of Gates (not including memories, IP Blocks)
a:	Less 100K Gates	
b:	100K to 500K Gates	
c:	500K to 1000K Gates	
d:	1000K to 2000K Gates	
e:	2000K to 3000K Gates	
f:	Above 3000K Gates		

5.4	Number of IO pins	
a:	No. of Functional IO pins	
b:	No. of Power IO pins	
c:	Total no. of IO pins:		

5.5	Expected Die size:	
	
5.6	Memory Requirements (Specify . if any):		

5.7	Special Cell / IPs (Specify . if any):		

5.8	Speed requirements / Max frequency: 		

5.9	Clocking Complexity (Specify):	
a.	Number of clock domains:	
b.	Skew requirements:	

5.10	Expected Power consumption	:	

5.11	Operating temperature:	

5.12	Junction temperature (estimate):	

5.13	Case temperature:	

5.14	Expected Packaging Solution:	

5.15	Voltage Requirements (Specify):	
a.	Core Voltage:
b.	I/O Voltage:
c.	Voltage Tolerance needed?:
d.	Specialized I/O needed? (eg: SSTL, PECL, LVDS, etc) (Pls Specify):
 

6.0	Testing Methodologies	
a.	JTAG	
b.	Boundry Scan	
c:	BIST	
d:	DFT	
e:	Others (List Below)		


7.0	Design Environment	
a:	UNIX / Version	
b:	Solaris / Version	
c:	NT / Version		


8.0	Design Tools used	
a:	Synopsys	 
b:	Cadence	
c:	Mentor Graphics	
d:	Monterrey	 
e:	FPGA . Xilinx	
f:	FPGA - Altera	
g:	Others (List Below)