Custom Layout Design Engineer

Job Description & Requirements

• Self-motivated.
• Good verbal and writing communication skills.
• Experience with the following tools: Cadence Virtuoso (Layout), PVS, Calibre Verification.
• Background in analog layout designs like ADC, DAC, oscillators, regulators, PLLs, op-amps, comparators, current mirrors, active-loads, voltage regulators, charge pumps, etc.
• Fullchip or block level Integration of mixed signal GDS.
• Strong problem solving ability.
• Deep sub-micron process design experienced. Up to 14nm is preferable.
• Understanding of circuit principles as affected by layout such capacitance, speed, noise & electro migration.
• Willing to travel and relocate.
• Work on custom analog, digital and mixed signal layout IPs such as ADC, DAC, oscillators, regulators, LDO, DC-DC and PLLs.
• Capable of block or fullchip level floorplanning in analog/mixed signal design.
• Have done multiple tapeouts and proven record of designing complex ICs/IPs in state of the art CMOS process technologies and has successfully placed products/IPs into production, preferably multiple times.
• High level proficiency in performing physical verification check (DRC, ERC, LVS, ANTENNA rules) with PVS/Calibre tools.