Project Description

Requirements

  • Graduates from Electrical Engineering (EE) or Computer Science (CS).
  • Strong background in ASIC design methodology and EDA tools for simulation and verification, synthesis, P&R, formal verification and static timing analysis.
  • Strong coding skill in verilog/VHDL RTL and behavioral code, experience with SystemVerilog will be a plus.
  • Experience with design through complete from RTL to GDS flow and familiar with ECO flow.
  • Familiar with Linux Environment (including shell scripting and linux gnu tools).
  • Scripting language experience a plus (perl, ruby, tcl, etc.)
  • Have successfully defined, developed, and implemented digital logic.
  • Ability to travel is a plus.
  • Familiarity with Cadence/Mentor Graphics/Synopsys environment is a plus.
  • Working experience in FPGA design and development software.
  • Highly self-motivated and excellent in problem solving and time management skills.
  • Able to work independently and in a team environment.

Responsibilities

Responsible included all technical aspects from feasibility to specification. Design documentation to meet architecture goals. Design logic solutions as per architectural specs. Understand the ASIC design flow, design verification flow, and integration flow. Development and debug of the verification environment. Definition and development of new designs as well as other front-end tasks. Front-end implementation tasks which include block or full-chip level design and verification, synthesis, timing analysis, timing closure, formal verification and power analysis. Work and collaborate with team members including verification team and PnR team.

Job Description / Other Requirements

  • Strong background in ASIC design flow [RTL to GDS].
  • Strong coding skill in Verilog/VHDL for synthesis able RTL and behavioral modeling. System Verilog, Verilog-AMS is a plus.
  • Working experience in FPGA design, debugging.
  • Strong verification skills using SVA, UVM, OVM, DFT.
  • Scripting language experience a plus (perl, Makefile, bash, tcl, … etc.).
  • Familiar with C coding, MATLAB is a plus.
  • Familiar with ECO flow, FMEA is a plus.
  • Able to work independently and in a team environment. Able to lead projects/team.

To apply for this position, kindly send an email with your resume to careers@symmid.com

A team of 20 Years of Experience

Symmid has a management team with collectively 20 years experience on average and have worked and serviced customers throughout the global semiconductor market e.g. China, Taiwan, UK, Germany and US. We look forward to grow with the right partners and want to leverage on Malaysian IC designers to serve these growing markets.